1. Field of the Invention
The present invention relates to a delay circuit, and more specifically to a delay circuit for delaying a predetermined time with respect to a reference clock signal a control signal to be sent to a control object (a tri-state buffer etc., to set the timing of a signal fed from an IC to the outside so as to satisfy predetermined conditions, for example).
2. Description of the Prior Art
Referring to FIGS. 4A and 4B, there are illustrated a circuit diagram of a prior delay circuit of the type described above and a control target of the same, respectively. In FIG. 4A, numeral 1 indicates a delay section composed of a plurality of inverters 1a through 1d connected in series to each other, from which an input signal B as a reference clock signal is outputted as a signal Bd, delayed a predetermined time interval. Numeral 2 indicates a NAND gate which receives the signal B as one input and the signal Bd as the other input, and outputs a NAND signal between both signals as a signal C. Additionally, in FIG. 4B numeral 3 indicates a tri-state buffer which receives X as an input signal and the foregoing signal C as a control input, and which outputs Y as an output signal.
Referring to FIG. 5, a operation timing chart of FIG. 4 is illustrated. Herein, the reference clock signal B, which is not illustrated, is generated by halving the frequency of a clock signal A, the frequency being twice that of the reference clock signal B.
In the following, there will be described the prior delay circuit shown in FIG. 4. The delay circuit is to output the input signal X as a signal Y with the assumption that the control signal C to the tri-state buffer 3 is valid from the time t.sub.2 a predetermined time interval .DELTA.t after the leading edge of the reference clock signal B to the trailing edge of the same signal B.
The operation will be described further in detail on the basis of the timing chart of FIG. 5. Once the reference clock signal B changes from `L` to `H` at the time t.sub.1, the change is delayed by the delay section composed of the plurality of the inverters 1a through 1d of FIG. 4, and the signal Bd changes from `L` to `H` a certain time after the time t.sub.1. Hereby, the two inputs B, Bd of the NAND gate 2 change together to `H`, and output C of the same changes from `H` to `L`. It is assumed that the time the signal C changes from `H` at the time t.sub.1 to `L` is .DELTA.t.sub.a. This is substantially determined by the delay time in the delay section 1. As the control signal C changes to `L`, or becomes valid, the tri-state buffer 3 of FIG. 4B is switched on to permit the input signal X to be outputted at the time t.sub.2 as the signal Y. It is assumed as .DELTA.t.sub.b a time interval from the time the control signal C becomes `L` to the time the signal Y is settled to `H` or `L`. Successively, as the clock signal B changes from `H` to `L` at the time t.sub.3, the output C of the NAND gate 2 immediately changes from `L` to `H` to cause the tri-state buffer 3 to be off with its output being high impedance. It is assumed a time interval from the time t.sub.3 to the time the output of the tri-state buffer 3 changes to high impedance is .DELTA.t.sub.c. The interval .DELTA.t.sub.c is relatively shorter than .DELTA.t.sub.b.
The prior delay circuit constructed as described above however has the following problems.
Generally, switching speeds of transistors as basic elements of various circuits are changed according to variations of power supplies and of temperature, and particularly affected by variations of supply voltages. Such a switching speed is faster as the supply voltage is higher, and oppositely it is instead slower as the same voltage is lower. Accordingly, the time interval .DELTA.t.sub.a from the building-up of the reference clock signal B to the time the control signal C is `L` (valid) or the time interval .DELTA.t.sub.b from the time the control signal C is `L` to the time the tri-state buffer 3 of FIG. 4(B) is switched on to establish the signal Y is shorter as the supply voltage is higher or vice versa. There is accordingly produced a problem that the time interval .DELTA.t from the time t.sub.1 of the building-up of the reference clock signal B to the time t.sub.2 of the establishment of the signal Y is severel varied as the supply voltage is higher and lower. Herein, .DELTA.t.sub.c shown in FIG. 5 does not have such a problem although it is also changed as the supply voltage becomes higher and lower, because it is inherently small in itself.
In view of the drawbacks with the prior art, it is an object of the present invention to provide a delay circuit capable of reducing to the utmost the width of variations of delay time as a target of control where the delay time might be shifted from a set value owing to supply voltage and the like becoming higher and lower.